-- 32 bit version register file
-- evillase

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY latch32 IS
   PORT
   (
      enable    : IN STD_LOGIC;
	  data 		: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      q         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
   );
END latch32;
ARCHITECTURE maxpld OF latch32 IS
BEGIN
latch : PROCESS (enable, data)
      BEGIN
         IF (enable = '1') THEN
            q <= data;
         END IF;
      END PROCESS latch;
END maxpld;
